GPS GRANDMASTER WITH ARM EMBEDDED LINUX AND SNMP

Janani
19. January 2022 · Write a comment · Categories: ARM, Embedded System, Linux

The process of checking and verifying that the system clocks of computers are in sync with the time source is known as time synchronization. Nowadays, with a large number of contemporary computers spanning across locations and are performing time-critical operations, it is essential to have the clocks are synchronized and accurate with in the order of few tens of Nano-seconds. Some of the use cases for such a it might be necessary to time stamp event occurrences, co-ordination of media broadcasting, phase corrections in small cell base stations, power generation, air traffic control, timing stock trading. One of the easiest and proven mechanisms is the use the constellations of GPS/GNSS satellites and create a globally acceptable clock with high accuracy.

The key components of Time synchronization are Grandmaster, Master and slave.

The Grandmaster clock is the major time source in a multi-clock network, sending time downstream to other master clocks. It has exceptionally accurate timing synchronization.
There could be options Master clocks acting as distributor aligning Grandmaster and slave clocks.
A slave clock is a device or clock that synchronizes with the master clock but does not provide timing.

In this blog, with the advent of powerful embedded systems, we will discuss in detail about the GPS grandmaster and realizing it with a low-cost ARM based Embedded Linux system and the associated technologies.

GPS Grandmaster

As mentioned, Grandmaster clock is the primary source of clock in the network. Some of the major features expected of a Grandmaster includes:

Accuracy – This is the most important feature of Grandmaster, and it is determined by system design, timestamping accuracy, and many algorithms such as BMCA (Best Master Clock Algorithm) and processes that run in the system (e.g., filtering, servo, etc).
Scalability – It refers to the overall number of physical interfaces a Grandmaster can have as well as the number of clock instances it can handle.
Resiliency– It is the capacity to handle numerous timing inputs that act as alternate time sources.
Portability – Sometimes it is essential to have the Grandmaster mobile.

Today, every part of the world is practically covered with Global navigation satellite systems (GNSS)such as USA’s NAVSTAR Global Positioning System (GPS), Europe’s Galileo

Today, every part of the world is practically covered with Global navigation satellite systems (GNSS)such as USA’s NAVSTAR Global Positioning System (GPS), Europe’s Galileo, Russia’s Global’naya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Indian Regional Navigation Satellite System (IRNSS), China’s BeiDou Navigation Satellite System. These satellites not only provide navigation data but also are time-transfer systems. Even a low-cost GPS receiver can provide accurate time information with stability very close to one part in ten to the fourteenth over one day (1ns/day).

Grandmasters can be created with such GNSS/GPS based receivers. A typical, GPS Grandmaster architecture looks like as shown in the below diagram

GPS Grandmaster - Block Diagram — GPS Grandmaster – Block Diagram

GPS-PPS Synchronization

Typically, GPS receivers provides the time of the day (ToD) information over a serial interface such as RS232/USB Serial as NMEA text. As this is not sufficient to synchronize, the GPS receivers provide a synchronization mechanism called pulse per second (PPS). This pulse, which has a rising edge synchronized with the GPS second, is of high accuracy, and can be used to discipline local clocks in order to keep them in sync with Universal Time (UT).

With a capable timing system inside the embedded Linux, it is possible to maintain the system clock with in few Nano-seconds of UT. With the system clock synchronized, now it has to be transferred to the slaves via a standard mechanism such as PTP or NTP.

NTP Server

One of the early and widely used Time Synchronization protocols is NTP – Network Time Protocol. The hierarchical architecture of NTP is divided into strata. Atomic clocks, like those in GNSS satellites, and GPS are examples of stratum 0 devices at the very top. Stratum 1 servers, also known as primary time servers, have a one-on-one direct link with a Stratum 0 clock, can achieve microsecond-level synchronization with Stratum 0 clocks, and can connect to other Stratum 1 servers for quick sanity checks and data backup. For tighter synchronization and increased accuracy, Stratum 2 servers can link to numerous primary time servers. NTP can support up to 15 strata, although each one reduces client synchronization by a little amount compared to Stratum 0.

Because NTP networks are software-based, all timestamp queries must wait for the local operating system, they have more latency and poorer accuracy. NTP provides a precise enough time resolution for most enterprises to settle conflicts quickly, but those requiring a much higher level of synchronization need to go for more precise PTP.

PTP Server

PTP, or Precision Time Protocol, is a network-based time synchronization standard that aims at nanosecond or even picosecond-level synchronization rather than millisecond-level synchronization of NTP.

Vis a vis NTP’s software-based approach, PTP timestamping is particularly precise because it uses hardware timestamping.

A total of four messages are exchanged between the master and slave in every PTP sequence:

The master’s first sync message to the slave
A slave to master sync message is sent as a follow-up
A message from the slave to the master requesting a postponement
The master sends a final delay response message to the slave

There are four different timestamps produced by this sequence:

T1 is the time when the master sends the first sync message
T2 is the time when the slave receives the first sync message
T3 is when the slave requests a delay
T4 is when the delay request is received by the master

During the delay response phase, the master delivers all four timestamps to the slave, and the slave can calculate the network latency between the master and slave in both directions.

IEEE 1588 enabled Ethernet PHY

As mentioned earlier, PTP needs a dedicated hardware time stamping mechanism. This is possible with single-chip Ethernet Physical Layer Transceiver (PHY) that are provided with IEEE 1588 based timestamping. While these are very similar to conventional Ethernet PHY’s, they have high precision timer that can timestamp transmission/receive packets in pico-second resolution. Some of the 1588 enabled PHY’s includes are Renesas UPD60611, Microchip KSZ8441, TI DP83869HM, Broadcom BCM81384 etc.

Embedded Linux based Grandmaster

Earlier days, it called for very powerful dedicated system to achieve time synchronization. Nowadays, even low-cost systems have enough power to act as Grandmasters. It is possible to achieve the high precision with some support from hardware such as IEEE1588 based timestamping. There is a plethora of open-source projects addressing the needs and it is quiet easy to create Embedded Linux based Grandmaster systems.

Some of the utilities that can be used are :

Ptp4l

Ptp4l is an IEEE-compliant implementation of the PTP. It implements both network master and slave clocks. For Grandmaster implementation, the master functionality can be used which will consider system clock as reference clock. Typical output of Ptp4l running as master on eth0 port is as follows:

ptp4l[1760.714]: port 1 (eth0): LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES

ptp4l[1760.715]: selected local clock 0e8a76.fffe.6b8917 as best master

ptp4l[1760.715]: port 1 (eth0): assuming the grand master role

Phc2sys

Phc2sys is an application that synchronizes the system clock with a PTP hardware clock (PHC).

PHC follows PTP time in hardware time stamping mode, while the system clock follows UTC time. phc2sys maintains the time difference between these two clocks in nanoseconds

Ts2PHC

ts2phc can be used to synchronizes PTP Hardware Clocks (PHC) to external time stamp signals. A single source may be used to distribute time to one or more PHC devices.

In addition to above tools, testp2p utility can be used to perform various operations such as driving external signal at PPS, setting/getting PTP time and date etc.,

With the GPS/PPS inputs, it will be possible to synchronize the Realtime clock to globally accepted accurate time. The PTP server can serve this time to other slaves.

Running phc2sys will produce the following output :

CLOCK_REALTIME phc offset 1635162324159518479 s0 freq +0 delay 160546

CLOCK_REALTIME phc offset 1635162324159518096 s1 freq –375 delay 160606

CLOCK_REALTIME phc offset 0 s2 freq -375 delay 160606

CLOCK_REALTIME phc offset 8 s2 freq -367 delay 160545

CLOCK_REALTIME phc offset 12 s2 freq -368 delay 160540

CLOCK_REALTIME phc offset -25 s2 freq -365 delay 160541

…

As it can be seen the time offset between the PHC and the System clock is shown in the offset information. The System clock is synchronized if the offset is continuously less than 30 ns.

The offset is kept within a nanosecond range of +/-50 nanoseconds. The clock servo states are indicated by the s0, s1, and s2 strings:

s0- unlocked
s1- clock step
s2- locked

The clock will not be stepped until the Servo state is locked (s2) (slowly adjusted). The freq value is the frequency adjustment of the clock in parts per billion (ppb).

NTP servers too, synchronize the NTP client with server time (Stratum 1).

Other management protocols such as SNMP can be used to monitor various clocks in the system and their characteristics like accuracy, precision, resolution, current synchronization states etc.

About Embien

Embien Technologies is a high-tech services provider in the embedded systems segment catering to such niche requirements. We have helped customers achieve sub- 30 nanoseconds compliance for PTP and sub-100 microseconds accuracy for NTP with Linux based embedded systems. Our other credentials include GPS anti-jamming system development, MIR-DIAL- Mid-infrared differential absorption LIDAR systems etc.

Instrument Cluster Design for Electric Vehicles with Renesas RL78

Arun Kumar V
30. September 2021 · Write a comment · Categories: ARM, Embedded Hardware, Embedded Software, Sparklet GUI Library

In any vehicle, the instrument cluster forms a critical part as it is the face of the vehicle that reflects the current state. Apart from providing the basic vehicle information, it can also provide crucial indications of electrical component malfunctions (EFI /ISG related). Clusters can acquire vehicle data over simple mechanisms such as encoders as well as through complex interfaces such as CAN, SAEJ1850 etc.,

Instrument cluster design for electric vehicles may have less system complexity, but they have to be more user friendly, less power hungry, and a cost-effective solution. Careful design and choice of cluster components is necessary to meet the stringent compliance requirements. Of the constituent components, the MCU holds the major stock whereas only a few vendors will be supporting automotive grade with the desired feature sets.

Renesas RL78 is an ultra-low power microcontroller (MCU) that enables customers to build compact, energy efficient instrument clusters for a wide range of two-wheeler and four-wheeler vehicles. It offers highly suitable peripheral interfaces such as: Three Channels of Stepper Motor Controller, LCD controller, Multiple IOs etc.,

In this blog, we will discuss in detail about the various features of an instrument cluster and how RL78 MCU will help simplify the design.

Instrument Cluster Subsystem

The major components and their functionalities are as follows:

Gauges: Generally, three gauges namely RPM, Temperature and Fuel Level get indicated by the cluster.
- Fuel Gauge: The Fuel gauge ranges from Empty (E) to Full (F). Typically, the Fuel sensor unit is a TSR /SMR type realized with components such as float with potentiometer, Adjustable arm and sending unit with two wires (signal & ground wire). The signal received from the fuel sensor is analog. The pointer position depends upon the incoming resistance value and indicates the vehicle’s fuel level.
- RPM Gauge: The signal received from the RPM sensor from encoder such as tach terminal unit with signal & ground wire, fire wall grommets is treated as frequency input. Based on the type and top speed of the vehicle, the input range varies.
- Temperature Gauge: The signal received from the temperature sensor is also analog. Realized with sensors such as protective rubber unit, thermistor with two wire. Front end circuit converts the input resistance to corresponding voltage and thereby the voltage value at the microcontroller input indicates the current engine temperature.
- Seven Segment Displays: Clusters may have different type of segmented display with various resolutions such as 27 X 4, 39 X 4, 48 X 4, 53 X 4 and 54 X 4. These could indicate information such as odometer, trip distance, hour meter etc.,
- Telltales: Telltales are sort of regulatory indications typically realized with LEDS required to show the state of various components such as low battery, engine faults, high beam etc. They are usually realized via onboard LEDs with mechanical light guide. Graphical overlays will also be placed over the guides with standard Tell tale signs.
- Switches: Usually a single switch or simple rotatable push-type switches are available to manipulate the information shown in the display such as Trip distance, Time etc.

There could be variations in the offerings and feature set based on the vehicle manufacturer.

RENESAS RL78 for Cluster:

Renesas is a leading semi-conductor company in the automotive space offering cluster solutions for many decades. While there are some architectural differences between all the MCU’s of the Renesas RL78 family, the sub-system remains more or less the same. The high-level design of the RL78 MCU based instrument cluster is captured below:

Instrument Cluster - Block Diagram — Instrument Cluster – Block Diagram

RL78 series of MCU’s help realize vehicle clusters effectively with its feature rich peripherals set:

Microcontroller: The RL78 MCU helps in achieving the highest performance within the low end MCU space. It offers improved efficiency, extensive scalability and reliable safety functions that aid in developing energy efficient instrument clusters. It has an operating voltage that ranges from 2.7V to 5.5V and flashes the program using 80 microcontroller pins.

Stepper Motor Drivers: There are up to three channels of stepper motor controllers / drivers with zero-point detection that can be configured using PORT pins (Sin+, Sin-, Cos+, Cos-). Each channel is controlling a stepper motor dedicated to gauges which commands the motor to move and hold at one of the angles without any position sensor. With the help of software based PID control, it is possible to effectively control the needles.

Segment LCD Controller: Capable of driving up to 200+ segments, the in-built LCD controller is available for controlling the segmented display with various resolutions such as 27 X 4, 39 X 4, 48 X 4, 53 X 4 and 54 X 4 which is directly driven from the RL78 microcontroller. The LCD screen can be controlled by the software to display any kind of data dynamically such as TRPI information, hour meter data etc.

Multiple IOs: There are multiple analogs and digital IOs available for interfacing sensors and Tell-Tale LEDs. RPM, temperature, and fuel level sensors are interfaced via a suitable front-end circuit. If needed, various Tell-Tale LEDs such as turn left, turn right, service, brake, etc. can be driven with dedicated digital outputs.

Analog Input Gauges: RL78 series comes with a rich set of ADC inputs that can be used to convert resistance/voltage-based sensor inputs to digital values. Software based processing will increase the accuracy of the acquired value.
Encoder inputs: With up to 24 timers, RL78 can be used to measure a variety of encoder inputs such as RPM, perform custom processing and obtain accurate digital values.
External connectivity: RL78 can also support I2C/SPI interfaces that can be used to communicate with peripherals such as EEPROM where the accumulated vehicle information such as ODO, TRIP data can be stored. RTC can be interfaces to track real time.

Variants of RL78 also offers sound generator which can set a volume level and tone frequency, two channels of CAN, and expanded flash memory/RAM up to a maximum of 512 KB/24 KB, suitable for low-end instrument cluster applications.

Embien’s Expertise in the Automotive Industry:

Embien Technologies is a leading embedded systems development company that specializes in high – tech product engineering services. We help clients take competitive lead in their markets. With a unique mix of innovation, technology, and quality, we offer cutting-edge automotive electronics system designs by adapting the latest technologies in clusters, diagnostics, infotainment, connectivity etc., With deep domain expertise, we have assisted several OEMs, Tier 1, and Tier 2 vendors to surge their automotive electronics such as Instrument Clusters (Heavy & Light- Duty Vehicles), Digital Cockpits etc., by integrating sensors & radars, network connectivity, path planning & mapping technologies. Do you have a design idea in mind? Then, get in touch with us today!

Interrupt Handling in ARM Cortex M

Saravana Pandian Annamalai
25. April 2019 · Write a comment · Categories: ARM, Embedded Software

In our earlier blogs on ARM Interrupt architectures, we explored the ARM exception models and registers. Also, we went through different kinds of Interrupt controllers being used. In the upcoming blogs, we will primarily see ARM Interrupt handling from the firmware/software perspective including operating systems like FreeRTOS, Linux and WinCE. To being with, this blog will discuss interrupt handling in ARM Cortex M MCUs.

Cortex M Vector Table

As discussed earlier, the ARM Cortex M series of MCUs typically carters to lower end application with the core running between a few MHz to a maximum 150MHz. To target low cost tools and ease of development, the interrupt architecture is designed to be simpler and straight forward. The vector table in ARM Cortex M series looks like:

Typically, on power-on reset, the Vector table base address is defined to be at 0. The ARM core, up on boot up, loads the stack pointer with the value stored at offset 0. And then it loads the Program counter with the address available at offset 4 and starts executing the same.

Thus, the vector table design is such that the stack is operational before the core starts executing thereby eliminating the need for an assembly code to set things up for calling functions. In the firmware perspective, this is a major advantage. There is no need to write any assembly code.

Following these 2 words, the table should hold the addresses of the exception handlers. The first 14 of them are pre-defined ad reserved for handling specific to the core and its execution. From offset, 0x40, the SoC specific interrupt handlers are defined and can be customized by the silicon vendor.

It can also be noted that there is a priority associated with each of these exceptions. Lower the number the higher the priority. Some of the major exceptions defined by ARM are

Reset Handler

At the highest priority of -3, this is the entry point of execution. Loaded to PC on power on reset, this is responsible for initializing the system peripherals and start executing the firmware/OS.

NMI Handler

At a priority only next to Reset Handler (-2), as the name suggests this cannot be masked by software. It is typically triggered by a specialized peripheral unit that can be connected to a critical functionality.

HardFault Handler

This exception is caused when there is an error during exception processing. At a higher priority of -1 than other exception, this can be used to recover from issues during exception handling.

MemManage Handler

Caused due to memory protection faults, the priority level can be configured by the firmware.

BusFault Handler

Caused during to memory access – either during instruction fetch or data access, the priority level can be configured by the firmware

UsageFault Handler

Caused during to instruction executing, the priority level can be configured by the firmware. The handler is called when one of the following errors occurs

Presence of an undefined instruction
Performing an illegal unaligned access
Core in invalid state on instruction execution
An error occurring on exception return.
Doing an unaligned address on word and halfword memory access
Performing division by zero

SVCall Handler

Known as the Supervisor Call, this handler is called up on the core executing a SVC instruction. This is typically used in OS environments to execute system services.

PendSV Handler

This is typically used in OS environments to perform context switching.

SysTick Handler

The ARM Cortex M core defines a specialize timer module to keep track of the System time. This handler is executed once this timer value reaches 0.

With this understanding of Cortex M vector table, now we will see how the firmware handles exceptions in software.

Cortex M Vector Table

To practically understand Cortex M Interrupt handling, we will take an example of software implementation of FreeRTOS running on NXP K66 MCU compiled using GCC tool chain. The first and foremost step is to define the vector table and place it in the Vector base location. The vector table for the device looks like this:

__attribute__ ((used, section(“.isr_vector”)))

void (* const g_pfnVectors[])(void) = {

// Core Level – CM4

&_vStackTop, // The initial stack pointer

ResetISR, // The reset handler

NMI_Handler, // The NMI handler

HardFault_Handler, // The hard fault handler

MemManage_Handler, // The MPU fault handler

BusFault_Handler, // The bus fault handler

UsageFault_Handler, // The usage fault handler

0, // Reserved

SVC_Handler, // SVCall handler

DebugMon_Handler, // Debug monitor handler

0, // Reserved

PendSV_Handler, // The PendSV handler

SysTick_Handler, // The SysTick handler

// Chip Level – MK66F18

DMA0_DMA16_IRQHandler, // 16 : DMA Channel 0, 16 Transfer Complete

DMA1_DMA17_IRQHandler, // 17 : DMA Channel 1, 17 Transfer Complete

DMA2_DMA18_IRQHandler, // 18 : DMA Channel 2, 18 Transfer Complete

UART0_RX_TX_IRQHandler, // 47 : UART0 Receive/Transmit interrupt

CAN1_Tx_Warning_IRQHandler, // 113: CAN1 Tx warning interrupt

CAN1_Rx_Warning_IRQHandler, // 114: CAN1 Rx warning interrupt

CAN1_Wake_Up_IRQHandler, // 115: CAN1 wake up interrupt

}; /* End of g_pfnVectors */

As it can be seen, the interrupt handlers are clubbed together as an array with the address to the top of the stack (lowest address as it grows towards higher address) as the first element. This array is placed in address 0, via linker script mechanism. In this example, using the section (.isr_vector) keyword, the location of the vector table is set to 0.

Also, it can be noted that there are hundreds of interrupt handlers supported. Even this example has close to 115 handlers. Obviously, a firmware system will not have all these implemented, hardly 20-30 interrupts will be used in a system. Instead of asking the user to define handlers, the start-up code provided by the silicon vendors, will have dummy functions (a while (1) loop) defined with weak reference.

weak void NMI_Handler(void)

{ while(1) {}

}

WEAK_AV void SVC_Handler(void)

{ while(1) {}

}

So, when the developer defines an interrupt handler with the same name in his code, this weak function will be discarded and user-defined function linked against instead.

Cortex M Interrupt Handling

With the vector table installed, the functions that are needed can be added one by one in the firmware. As a first step, the Reset Handler has to be created. At typical, reset handler will look like as below.

void ResetISR(void) {

// Disable interrupts

__asm volatile (“cpsid i”);

// If __USE_CMSIS defined, then call CMSIS SystemInit code

SystemInit();

// Copy the data sections from flash to SRAM.

unsigned int LoadAddr, ExeAddr, SectionLen;

unsigned int *SectionTableAddr;

// Load base address of Global Section Table

SectionTableAddr = &__data_section_table;

// Copy the data sections from flash to SRAM.

while (SectionTableAddr < &__data_section_table_end) {

LoadAddr = *SectionTableAddr++;

ExeAddr = *SectionTableAddr++;

SectionLen = *SectionTableAddr++;

data_init(LoadAddr, ExeAddr, SectionLen);

}

// At this point, SectionTableAddr = &__bss_section_table;

// Zero fill the bss segment

while (SectionTableAddr < &__bss_section_table_end) {

ExeAddr = *SectionTableAddr++;

SectionLen = *SectionTableAddr++;

bss_init(ExeAddr, SectionLen);

}

// Reenable interrupts

__asm volatile (“cpsie i”);

main();

// main() shouldn’t return, but if it does, we’ll just enter an infinite loop

while (1) {

;

}

This minimalistic handler, disables all interrupts up on entry, configures the core and major peripherals via SystemInit function. Then it initializes the data and bss sections. Finally, it enables the interrupts before jumping to the main function.

Now we will see how a peripheral is configured for interrupt operation based on the Systick unit.

uint32_t SysTick_Config(uint32_t ticks)

{

if ((ticks – 1UL) > SysTick_LOAD_RELOAD_Msk)

{

return (1UL); /* Reload value impossible */

}

SysTick->LOAD = (uint32_t)(ticks – 1UL); /* set reload register */

NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) – 1UL); /* set Priority for Systick Interrupt */

SysTick->VAL = 0UL; /* Load the SysTick Counter Value */

SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

SysTick_CTRL_TICKINT_Msk |

SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */

return (0UL); /* Function successful */

}

As the code listing shows, the function configures various registers needed for proper operation of the Systick interrupt such as LOAD, VAL, CTRL etc. IT=t also configures the priority of the interrupt. As mentioned earlier, in Cortex M architecture, each of the interrupts has an associated priority. Depending on the implementation, there could be n number of bits corresponding to each interrupt number. Lower the number, higher the priority/urgency and can be set via the NVIC_SetPriority CMSIS API. With this mechanism, it is possible for the interrupts to be prioritized and only the higher priority one will be serviced if more than one interrupt is pending at the same time.

Typical handler for SysTick looks like:

void SysTickHandler( void )

{

/* The SysTick runs at the lowest interrupt priority, so when this interrupt

executes all interrupts must be unmasked. There is therefore no need to

save and then restore the interrupt mask value as its value is already

known. */

portDISABLE_INTERRUPTS();

{

/* Increment the RTOS tick. */

if( xTaskIncrementTick() != pdFALSE )

{

/* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */

portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;

}

portENABLE_INTERRUPTS();

}

Cortex M Interrupt Handling via Assembly

So far, we have not writing a single line of assembly code and still able to do all the required functionality in software. In some cases, there will be a need to do assembly code. In these cases, the handler can be defined as naked function (Which will not generate any stack push/pop and return codes) and implement them in assembly.

For example, in FreeRTOS, the SVC Handler implementation is as below:

void vPortSVCHandler( void ) __attribute__ (( naked ));

void vPortSVCHandler( void )

{

__asm volatile (

” ldr r3, pxCurrentTCBConst2 \n” /* Restore the context. */

” ldr r1, [r3] \n” /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */

” ldr r0, [r1] \n” /* The first item in pxCurrentTCB is the task top of stack. */

” ldmia r0!, {r4-r11, r14} \n” /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */

” msr psp, r0 \n” /* Restore the task stack pointer. */

” isb \n”

” mov r0, #0 \n”

” msr basepri, r0 \n”

” bx r14 \n”

” \n”

” .align 4 \n”

“pxCurrentTCBConst2: .word pxCurrentTCB \n”

);

}

Thus with compiler extensions, it is possible to include assembly based interrupt handling as well.

Switching Vector tables

In the above examples, we have noted that the vector table is located at address 0. But there are cases, where we will need to place it at a different location. For example, the flash location could be at address 0, and the RAM, where the user wants to place the vector table could be elsewhere. Or it could be a dual A/B firmware or a bootloader/application firmware each sitting at a different location. So, based on the current code being executed, the vector table location differs.

ARM provides a simple mechanism to switch the base address of the vector table. It provides a Vector table offset register at address 0xE000ED08 in the NVIC group, where the base address can be programmed. For example, to switch the vector location to address 0x20000000, following lines will suffice.