As discussed in the previous blog, the LEDs in a DMD panel are organized as small groups in a matrix form. With this the number of pins and power required are significantly reduced. But it is preferable to be able to control with 4-5 pins so that even an 8 bit MCUs can manage such display. This calls for a bit complex electronics in the panel and software in the MCU, but should be manageable in terms of cost and usability.

This blog covers the internal circuitry inside DMD in detail. The block diagram of the overall set up is depicted below.

Dot Matrix Display – Overall Setup Block Diagram

As it can be seen, there are shift registers and demulitplexers used to simplify the effort in MCU. The dual P-channel MOSFET feeds the positive supply voltage to the LED anodes which denotes the row control and the shift registers provides the return path for the LED’s which denotes the column control. The MCU controls the demultiplexer with GPIO interface and interfaces with the shift registers through serial interface, most commonly SPI. More details of them are covered below. For further explanation, we will consider a DMD panel of 512 LEDs, each row is a collection of anode of 32 LEDs and each column is a collection of cathode of 4 groups of 4 LEDs (one column of 16 LEDs divided into 4 groups each of 4 LEDs for reducing IO pins required). The following figure depicts the arrangement of 16X32 LED panel

16 X 32 DMD panel arrangement

Role of Serial Shift Register (74HC595)

The purpose of the shift register is to reduce the number of GPIOs required to drive the column of the LED matrix. 74HC595 is an 8-bit serial shift register with output latches and storage register.  The block diagram of the shift register commonly used inside DMD is given below (courtesy of 74HC595 datasheet)

Serial Shift Register – Block Diagram

With one shift register we get 8 GPIOs possible. Hence for driving 32 columns of 16 LEDs, (total 128 GPIOs) we require 16 serial shift register. SPI clock, SPI MOSI and a latch signal acts a shift register inputs. The main advantage of this serial shift register is that it outputs the serial input fed to it in its serial output pin only when the latch signal is provided. The serial output of the first shift register is connected to the serial input second register. Likewise 16 shift registers are cascaded in series resulting in 128 GPIO pins.

Each of the 128 pin will in turn control 4 LEDs in a column resulting 512 LEDs on the whole. The data to be displayed can be fed as a 128 bit data with 128 clock pulse to the serial shift register. The data will not appear on the output unless the data is transferred to the storage register. Only upon the positive transition of the latch signal, the data will be transferred to the storage register. The data will automatically appear on the output since the output enable pin is permanently grounded.

Since the shift register corresponds to the control of 4 groups of LEDs in 32 columns, the Demultiplexer IC is required to drive the LEDs in 16 rows corresponding to the required data bits.

The following figure depicts the serial shift register circuitry in 16X32 DMD panel, with 128 output lines. Each shift register outputs has 8 outputs, hence 16 shift registers are serially connected for 128 output lines for column control. One output line is connected to 1 group of 4 LEDs in a column. Hence 128 output lines will be connected to 128 groups of 4 LEDs across 32 columns (i.e. one column has 4 groups of 4 LEDs).

Serial Shift Register Circuit in 16 X 32 DMD panel

Role of Demultiplexer

Demultiplexer is dedicated for row control. 74HC138 is a 3 to 8 line demultiplexer with eight mutually exclusive inverting outputs. Out of three available address inputs only two inputs are selected for 4 individual inverting outputs. The four outputs from the demux will control the gates of four dual P-channel MOSFET where we get 4 pairs of drive outputs which in turn will drive the necessary current to the LEDs in the 16 rows. Finally there are 4 individual sets of multiplexed rows within the DMD. The block diagram of demultiplexer is depicted below (courtesy of 74HC138 datasheet)

Demultiplexer Block Diagram

With this arrangement only four rows will be illuminated at a time while the other is not illuminated. Hence the values of 4 outputs from the demux should be toggled periodically to illuminate all the sets of multiplexed rows. With persistence of human eye, if the LEDs are refreshed once around 20 ms, it is sufficient to show a flicker free display.

Following figure shows the four individual sets of the multiplexed rows inside DMD. The Color coding differentiates the 4 multiplexed rows and the four demux outputs are connected in the following manner

Y0 – connected to the rows R16, R12, R8, R4

Y1 – connected to the rows R15, R11, R7, R3

Y2 – connected to the rows R14, R10, R6, R2

Y3 – connected to the rows R13, R9, R5, R1

Multiplexed rows inside DMD

The demultiplexer input/output combination and the DMD row illumination sequence is illustrated in the following table

Example

1. Consider a 32X16 DMD panel
2. The following figures illustrates the sequence of bit shifting

A single data bit is shifted in to the DMD and it is effectively present in the [R16, C8] location.

First Bit shift into DMD

On further data in, the Old data moves one bit to [R16, C7] and new data bit is loaded at [R16, C8]

After 2nd bit input

After the input of 9th bit, the first bit is moved to the twelfth row at [R12, C8] and the bit 9 is loaded at [R16, C8]

After 9th Bit input

Similarly with 32nd bit input, the bit one is moved to the forth row at [R4, C1] and the bit 32 is loaded at [R16, C8]

After 32nd bit input

Upon the input of 33rd bit, the bit one is again moved to the sixteenth row but this time at [R16, C16] and the new bit 33 is loaded at [R16, C8]

After 33rd bit input

Likewise on input of 128 bits, the bit 1 is moved to the consecutive rows and columns till [R4, C25] and the bit 128 is loaded at [R16, C8]

After 128th bit input

Thus the entire pattern to be displayed can be loaded bit by bit. Running even at a low clock frequency of 8KHz, the 128 bits can be easily shifted in 16 ms, more than needed for human eye to detect the change.

DMD – Daisy Chain

It is possible to connect the multiple DMD panels in series using ribbon cables. This is called daisy-chaining. The number of the DMD in series is limited to the RAM size and the SPI clock frequency.
Even though the DMD can also come with multiple LEDs of varying color such as RED, GREEN, BLUE, etc, the underlying connection mechanism is same and each of the colored LED’s are controlled separately.

Now that we can control each LED of the DMD display independently, we can create any pattern to be displayed. In the upcoming blogs, we will discuss in detail about the software based control mechanism and creating rolling displays.