As discussed in the previous blog, the LEDs in a DMD panel are organized in a matrix form — significantly reducing the pin count and power requirements. To control a panel using only 4–5 pins (manageable even by an 8-bit MCU), the DMD display multiplexing shift register interface employs shift registers and demultiplexers. This blog covers the internal circuitry of the DMD display multiplexing shift register interface in detail — a key area of embedded device driver development for LED matrix displays. Embien's Industries team has implemented this DMD display multiplexing shift register interface across industrial signage, factory floor indicators, and transportation display systems.
The digital circuit design of the overall setup is depicted in the block diagram below.
Dot Matrix Display – Overall Setup Block Diagram
As shown, shift registers and demultiplexers simplify the MCU effort significantly. The dual P-channel MOSFET feeds positive supply voltage to the LED anodes (row control); the shift registers provide the return path (column control). The MCU controls the demultiplexer via GPIO and interfaces with shift registers through SPI — the heart of the DMD display multiplexing shift register interface. For further explanation, we consider a DMD panel of 512 LEDs: each row is a collection of anodes of 32 LEDs; each column is a collection of cathodes of 4 groups of 4 LEDs. The following figure depicts a 16×32 LED panel.
16 X 32 DMD panel arrangement
Embedded Device Driver Development: Serial Shift Register (74HC595)
The primary task in embedded device driver development for DMD is reducing the GPIO count needed to drive the LED matrix columns. The 74HC595 is an 8-bit serial shift register with output latches and storage register — the workhorse of embedded device driver development for the DMD display multiplexing shift register interface. Its block diagram (courtesy of 74HC595 datasheet):
Serial Shift Register – Block Diagram
Peripheral Drivers: SPI-Based Column Control
The peripheral drivers for the DMD shift register chain use SPI clock, SPI MOSI, and a latch signal as inputs. One shift register provides 8 GPIO outputs; for 32 columns of 16 LEDs (128 GPIOs total), 16 shift registers are cascaded in series. The main advantage: the register outputs the serial input only when the latch signal is applied — preventing partial-frame glitches. These peripheral drivers characteristics make the 74HC595 the standard choice for column control in DMD panels.
Each of the 128 pins controls 4 LEDs in a column — resulting in 512 LEDs overall. A 128-bit data stream with 128 clock pulses loads the display frame. Data only appears at the output on the positive transition of the latch signal, transferred to the storage register — the output enable pin is permanently grounded.
Serial Shift Register Circuit in 16 X 32 DMD panel
Digital Circuit Design: Demultiplexer for Row Control
The demultiplexer handles row control — a critical digital circuit design element in the DMD display multiplexing shift register interface. The 74HC138 is a 3-to-8 line demultiplexer with eight mutually exclusive inverting outputs. Two of the three address inputs are selected for 4 individual inverting outputs. These four demux outputs control the gates of four dual P-channel MOSFETs, providing 4 pairs of drive outputs for the 16 rows. This digital circuit design approach ensures only 4 rows are illuminated at a time, reducing peak power consumption significantly. The block diagram (courtesy of 74HC138 datasheet):
Demultiplexer Block Diagram
Custom Device Driver: Multiplexed Row Refresh Timing
The custom device driver for DMD must toggle the four demux outputs periodically to illuminate all row sets. With persistence of human vision, refreshing LEDs within 20 ms is sufficient for a flicker-free display. The custom device driver timing loop manages this refresh cycle — toggling the demux, loading the next row's 128-bit frame via SPI, and latching the output. The Electronic Circuit Design Services team at Embien designs these timing-critical embedded device driver development layers for production DMD systems.
The four multiplexed row sets in the DMD are connected as follows:
Y0 – connected to rows R16, R12, R8, R4
Y1 – connected to rows R15, R11, R7, R3
Y2 – connected to rows R14, R10, R6, R2
Y3 – connected to rows R13, R9, R5, R1
Multiplexed rows inside DMD
The demultiplexer input/output combination and the DMD row illumination sequence:
Example: Bit-Shifting Sequence in the DMD Display Multiplexing Shift Register Interface
The following figures illustrate the bit-shifting sequence in the DMD display multiplexing shift register interface for a 32×16 panel:
A single data bit shifted in is present at [R16, C8]:
First Bit shift into DMD
On further data input, old data moves one bit to [R16, C7] and new data loads at [R16, C8]:
After 2nd bit input
After the 9th bit, the first bit moves to [R12, C8] and bit 9 loads at [R16, C8]:
After 9th Bit input
After 128 bits, the complete frame is loaded. Even at 8 KHz SPI clock, 128 bits shift in 16 ms — well within the 20 ms refresh requirement. This is the fundamental principle of the DMD display multiplexing shift register interface.
After 128th bit input
DMD Daisy Chain
Multiple DMD panels can be connected in series using ribbon cables — a technique called daisy-chaining. The number of panels in series is limited by RAM size and SPI clock frequency. The DMD display multiplexing shift register interface scales linearly: each additional panel adds 128 bits to the SPI frame. Even panels with multiple LED colors (RED, GREEN, BLUE) use the same underlying digital circuit design — each color channel controlled separately. With this embedded device driver development approach, full-color daisy-chained DMD walls become feasible on low-cost 8-bit MCUs.