Overview

Sparklet is supported on RH850 series of microcontroller from Renesas. Optimized for Cluster use cases, these MCU’s has in-built GPUs that can support 2.5D graphics. Sparklet leverages the GPU which in turn depends on the GHS compiler and the RGL library, which are the pre-requisites for Sparklet to run on RH850 MCUs.

It is essential to understand the memory architecture in RH850, RGL and Sparklet to optimize the performance.

Below is the memory map of RH850 D1M1A. The MCU has 3 memory regions of interest:

GHS IDE

Memory map of RH850 D1M1A

  • Internal SRAM starting at address 0xFED80000 for a size of 512 KB.

  • Video RAM starting at address 0x3FD9C000 for a size of about 2.4MB.

  • External SDRAM starting at address 0x40000000 for a size dependent on the target board design.

RGL needs at least 4 memory regions for proper operations. For 3 of them, it employs Heaps and manages them via abstraction called the CDI Heap manager (r_cdi_memory.c).

The 4 memory regions are captured in the below table:

Memory Region

Usage

Heap Manager

Typical consumption

IRAM

For general CPU related operations

IramHeap

30KB

Video RAM

For allocating Video Memory/general operations

VramHeap

Based on configuration

External SDRAM

For allocating Video Memory/general operations

SdramHeap

Based on configuration

Message Queue Memory

For internal GPU queue operations

NA

Based on configuration in r_util_dhd.h

Sparklet internally uses these heaps to manage its memory so that there is a streamlined access to memory with the CDI Heap Manager remaining the sole master of the memory resource. For any memory assigned via memory pools in Flint, internally the memory block is allocated via the Heap Managers.

Sparklet uses memory pools to manage its memory as captured below.

Pool

Source Heap

Memory Region

Usage

Typical consumption

Internal SRAM

NA. Direct Memory via value

IRAM

For allocating widgets, lookup table etc. Set via BMEM_POOL_DEFAULT macro in rh850_bsp.c

Based on project size

Internal VRAM

VramHeap via Auto Alloc

Video RAM

Frame buffer configuration as set in Flint EFP -> Memory and Storage

Based on display resolution and configuration

External SDRAM

SdramHeap via Auto alloc option

External SDRAM

Frame buffer configuration as set in Flint EFP -> Memory and Storage

Based on display resolution and configuration

In addition to all these, there might be a need to use capture interface in the design which calls for a separate memory to be set aside for capture buffer. All these memory regions are configured via a single function called sgui_rh850_mem_init with arguments as below

Parameter

Source Heap

sgui_rh850_mem_init (uint32_t u32_rh850_iram_base_addr, uint32_t u32_rh850_iram_block_count, uint32_t u32_rh850_iram_block_size,

For IRAM Heap initialization

uint32_t u32_rh850_vram_base_addr, uint32_t u32_rh850_vram_block_count, uint32_t u32_rh850_vram_block_size,

For VRAM Heap initialization

uint32_t u32_rh850_sdram_base_addr, uint32_t u32_rh850_sdram_block_count, uint32_t u32_rh850_sdram_block_size,

For SDRAM Heap initialization

uint32_t u32_rh850_video_ram_base_addr, uint32_t u32_rh850_video_ram_size,

For DHD Message queue memory

uint32_t u32_rh850_capture_buf)

For capture memory setup

To give a fair idea, Sparklet does the following internally:

 1r_cdi_Heap_t IramHeap;
 2
 3r_cdi_Heap_t SdramHeap;
 4
 5r_cdi_Heap_t VramHeap;
 6
 7R_CDI_InitHeapManager ((uint32_t) u32_rh850_iram_base_addr, &IramHeap, 0, u32_rh850_iram_block_count, u32_rh850_iram_block_size); // for IRAM
 8
 9R_CDI_InitHeapManager((uint32_t) u32_rh850_vram_base_addr,  &VramHeap,  0,  u32_rh850_vram_block_count,  u32_rh850_vram_block_size); // for VRAM
10
11R_CDI_InitHeapManager((uint32_t) u32_rh850_sdram_base_addr,  &SdramHeap,  0, u32_rh850_sdram_block_count, u32_rh850_sdram_block_size); // for SDRAM
12
13R_UTIL_DHD_Config((dhd_gpu_ptr_t) u32_rh850_video_ram_base_addr, u32_rh850_video_ram_size, & IramHeap);
14
15R_SYS_DHD_SetCpuHeap(&IramHeap);

A recommended memory map is given below:

RAM pool

Base Address

Size

Count

IRAM

0xfeb88160

64

2048

VRAM

0x3fdbc880

512

2170

SDRAM

0x40000000

2048

6656

Message Queue RAM

0x3fd9c000

0x20880

flint_mem_efp

Memory allocation in Flint

RH850 specific API’s

Configuring Sparklet for RH850

Running Sparklet over RTOS

Running Sparklet Bare Metal

Camera Support in Sparklet

Compiling Sparklet on GHS

Optimizing Sparklet CPU usage